Description
The HP 1660A Series are 100-MHz State/500-MHz Timing Logic Analyzers.
- 68 logic analyzer channels in the HP 1662A
- Maximum State Speed: 100 MHz
- Minimum State Clock Pulse Width: 3.5 ns
- Minimum Master to Master Clock Time: 10.0 ns
- Minimum Glitch Width: 3.5 ns
- Maximum Conventional Timing Rate: 250 MHz full channel, 500 MHz half channel
- Maximum Transitional Timing Rate: 125 MHz full channel, 250 MHz half channel
- Maximum Timing with Glitch Rate: 125 MHz half channel
- Threshold Accuracy: ± (100 mV + 3% of threshold setting)
- Setup/Hold Time:
Single Clock, Single Edge 0.0/3.5 ns through 3.5/0.0 ns, adjustable in 500-ps increments
Single Clock, Multiple Edges 0.0/4.0 ns through 4.0/0.0 ns, adjustable in 500-ps increments
Multiple Clocks, Multiple Edges 0.0/4.5 ns through 4.5/0.0 ns, adjustable in 500-ps increments - Lightweight, passive probes for easy hookup and compatibility with previous Agilent logic analyzers and preprocessors
- Compare, chart, and waveform displays
- 3.5-inch disk drive
- HP-IB and RS-232C interface
- 4 kbytes deep memory on all channels with 8 kbytes in half channel mode
- Marker measurements: Time Interval, Delta States, Patterns, Statistics functions
- 12 levels of trigger sequencing for state and 10 levels of sequential triggering for timing
- 100 MHz time and number-of-states tagging
- Full programmability
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